1. Field of the Invention
The present invention relates to a technique to design a semiconductor device, and in particular, relates to a technique to perform an LPE (Layout Parameter Extraction) process for a layout of a semiconductor device.
2. Description of the Related Art
In designing a semiconductor device by using a computer (CAD system), layout design is carried out based on a netlist (information showing connection relationship between logic elements) after logic design is carried out. After a layout is determined, various types of verification processes are conducted to check whether the layout satisfies a design rule, or whether a device having the layout properly operates, and so on. An LPE (Layout Parameter Extraction) process is known as one process carried out in the verification process.
In the LPE process, extraction of a parasitic resistance and a parasitic capacitance (referred to as “parasitic RC” hereinafter) relevant to an interconnection in the obtained layout is carried out. Such a parasitic RC is a parameter that can be determined only after the layout is determined, and is not included in the netlist. Therefore, an extracted parasitic RC is added to the netlist, and the netlist containing the parasitic RC (referred to as “netlist with parasitic RC” hereinafter) is generated. That is to say, a tool for carrying out the LPE process inputs a netlist and a layout data, and outputs a netlist with parasitic RC.
After that, a delay verifying process and a timing verifying process are carried out for a device on the design by using the obtained netlist with parasitic RC. When the result of the verifying process indicates a “fail” state, the above layout design process is carried out again. Then, the LPE process and the verifying process are again carried out. The above processes are repeated until the layout “passes” the verifying process. If the result of the verifying process indicates a “passed” state, a final layout data is determined.
Japanese Laid Open Patent Application (JP-P2001-265826A) discloses a technique related to the LPE process. In a circuit simulation device disclosed in Japanese Laid Open Patent Application (JP-P2001-265826A), layout information of an integrated circuit is stored in a first storage section. Also, interconnection variations information is stored in a second storage section. Process information showing a manufacturing process of an integrated circuit is stored in a third storage section. An interconnection resistance and capacitance extracting section extracts interconnection resistance and capacitance in which variation are taken into consideration based on the layout information, the interconnection variations information, and the process information, and generates a netlist that includes the extracted interconnection resistance and interconnection capacitance. A simulation section inputs the generated netlist, and conducts a delay analysis of the integrated circuit in consideration of the interconnection variations.
As stated above, the LPE process is an important process requiring high accuracy to determine whether or not a designed semiconductor device properly operates. Here, in an actual manufacturing process of a semiconductor device, a structure of an interconnection and so on may not be manufactured as precisely as is intended. In other words, an interconnection layer width, an interconnection layer thickness, an interlayer insulating film thickness, and so on may possibly indicate variations from desired values. Such a variation is referred to as a “process variation” hereinafter. The process variation affect a delay in a circuit. Since the process variation may be caused, it is possible that an actual product does not operate properly, even if a designed layout passes an operation verifying process of the computer.
In the LPE process, therefore, it is desirable to extract the parasitic RC in consideration of the process variation. It is also desirable to conduct a verifying process for a plurality of netlists with parasitic RC in which the process variation is taken into consideration. Consequently, a layout data is produced that can cope with some extent of the process variation. If a product is manufactured based on the layout data, a probability that the product is defective is reduced even if the process variation is generated.
However, when the process variation is considered, time for carrying out the LPE process and the delay verifying process is greatly increased, as compared with a case where the process variation is not considered. As stated above, the process variation include variations of a plurality of parameters such as the interconnection layer width and the interlayer insulating film thickness, and the number of combinations of the variations is huge. It is virtually impossible to extract the parasitic RC and carry out the delay verifying process for all the combinations. The above conventional example (Japanese Laid Open Patent Application (JP-P2001-265826A)) gives suggestion of the LPE process and the verifying process taking the process variation into consideration. However, the conventional example does not describe a specific method of reducing the time for the LPE process and the verifying process. A technique is demanded that can reduce the time for semiconductor device design while considering the process variation.